The Best Kept Secret in Semiconductor Innovation: Backside Power Delivery

Read Below:

• Backside Power Delivery (BPD) revolutionizes chip architecture by relocating power interconnects beneath the wafer, cutting IR drop, boosting signal integrity and enabling >90% cell utilization in sub-2nm nodes.

• Intel, TSMC and Samsung are scaling BPD into AI, SoC and server chips, thus achieving up to 20% power savings and significant die shrinkage across A16, SF2Z and RibbonFET-powered platforms.

• McKinsey Electronics supports BPD adoption across the Africa, Middle-East and Türkiye region, offering Tier-One components and local engineering expertise for OEMs embracing next-gen power delivery designs.

Why Are the World's Most Advanced Chips Suddenly Being Powered from Behind?

As semiconductor technology approaches the 2nm threshold, traditional power delivery methods face significant challenges. Backside Power Delivery (BPD) emerges as a transformative solution, relocating power interconnects to the wafer's backside. This architectural shift addresses power integrity issues, routing congestion and performance limitations inherent in front-side power delivery.

Understanding Backside Power Delivery

In conventional chip designs, both power and signal interconnects reside on the front side of the silicon wafer. This configuration leads to competition for routing space, increased resistance and voltage drops. BPD reimagines this architecture by moving the power delivery network (PDN) to the wafer's backside, allowing for:

• Reduced IR Drop: Shorter, wider power paths decrease resistance, enhancing voltage stability.

• Improved Signal Integrity: Isolating power lines minimizes electromagnetic interference with signal paths.

• Enhanced Routing Density: Freeing front-side space allows for more efficient signal routing and increased transistor density.

Industry Adoption and Roadmaps

Intel: PowerVia and RibbonFET Integration

Intel's PowerVia technology exemplifies BPD's benefits. Integrated with RibbonFET gate-all-around transistors in the 20A and 18A process nodes, PowerVia has demonstrated:

• Over 90% cell utilization.

• A 5% frequency improvement.

• A 30% reduction in voltage droop in test chips.

TSMC: Super Power Rail (SPR) in A16 Node

TSMC plans to implement its Super Power Rail (SPR) BPD solution in the upcoming A16 process node, targeting mass production in late 2026. SPR aims to enhance logic density and performance by dedicating front-side routing resources exclusively to signals. Compared to the N2P fabrication process, A16 is expected to offer a performance improvement of 8% to 10% at the same voltage and complexity, or a 15% to 20% reduction in power consumption at the same frequency and transistor count.

Samsung: BPD in 2nm-Class Nodes

Samsung has reported successful BPD implementation in 2 nm-class test chips, achieving up to a 17% die area reduction and a 9.2% decrease in wiring length, contributing to improved performance and efficiency. The company's SF2Z process, slated for mass production in 2027, incorporates backside power delivery to enhance chip performance and power efficiency.

Technical Challenges

Implementing BPD introduces several manufacturing and design complexities:

• Wafer Thinning and Bonding: Achieving the necessary thinness for backside processing requires precise wafer handling and bonding techniques.

• Thermal Management: Relocating power networks affects heat dissipation pathways, necessitating new thermal solutions.

• Design Tool Adaptation: EDA tools must evolve to accommodate backside routing and new design rules.

These challenges require collaborative efforts across the semiconductor ecosystem to develop standardized processes and tools.

Real-World Impact Examples

BPD's benefits extend to various applications:

• AI Accelerators: Enhanced power delivery supports the high computational demands of AI workloads.

• High-Performance Mobile SoCs: Improved power efficiency and reduced die size are critical for mobile devices.

• Data Center CPUs: Better thermal management and power integrity are essential for server-grade processors.

Comparative Analysis

Future Outlook

As AI, high-performance computing, and mobile applications demand greater efficiency and performance, BPD stands out as a pivotal technology. Its adoption is expected to accelerate, with major foundries and design houses investing in its development. Continued innovation in materials, processes and design methodologies will be essential to fully realize BPD's potential in next-generation semiconductor devices.

With a regional office in South Africa, McKinsey Electronics supports engineering teams navigating the shift toward advanced semiconductor nodes by providing access to tier-one components that align with emerging technologies like Backside Power Delivery. As BPD adoption grows among leading foundries, local OEMs, and design houses across the region can leverage McKinsey Electronics’ on-ground technical engineering support and distribution network to source materials and components optimized for next-generation power architectures.

Contact McKinsey Electronics offices in South Africa for more details.